In today's semiconductor packages, a common packaging technology used is a so-called flip chip assembly in which a semiconductor die including a given component such as a processor, a chipset, memory, or the like, is coupled to a package substrate by interconnections such as conductive bumps, controlled collapse chip connection (C4) contacts or other such connections.
Because of the small size of the semiconductor die and its fast operating speeds, a great amount of heat may be generated. Accordingly, a semiconductor package typically includes a thermal solution such as an integrated heat spreader (IHS) which is typically adapted about the semiconductor die. Generally an interface material such as a thermal interface material (TIM) is coupled between the die backside and the IHS. Typically, the IHS is formed of a metal and the TIM may be a solder material such as indium (In). This TIM thus acts as a joint between the IHS and the die backside, which is typically a backside metal (BSM) layer.
Oftentimes, undesired effects exist at an interface between the TIM and the IHS, e.g., due to a reaction of metal plating on the IHS and the composition of the TIM. This can lead to interfacial delamination at the interface, potentially leading to failed devices, thermo-mechanical fatigue induced degradation and so forth. For example, an intermetallic compound (IMC) layer formed at the interface between TIM and IHS may form large scallops that can spall off during joint formation, leading to crack initiation and propagation during reliability testing, in turn increasing thermal resistance (Rjc) of the package, and causing failure of thermal requirements. Such effects become magnified at the smaller and thinner dimensions of current and future semiconductor devices.